1. Field of the Invention
This invention relates to a storage module in which a cell field is formed of single-transistor storage cells which are arranged between word lines and bit lines, in which the cell field is divided into two zones in that the bit lines are divided into two halves, in which a read out amplifier is arranged, in each case, between the two halves of each bit line and at least one blank cell is arranged in each zone of the cell field in respect of each half of the bit line.
2. Description of the Prior Art
Storage modules are well known in the art in which storage cells having transistors are arranged between word lines and bit lines. As an example of such an arrangement, one may refer to the publication "Electronics", Sept. 13, 1973, Pages 116 to 121. In these cell fields, a storage cell is in each case arranged at the intersections of word lines and bit lines. A storage cell can consist, for example, of a MOS transistor and a storage capacitor. Here, the controlled electrode of the transistor is connected to a word line, whereas an electrode of the controlled path of the transistor is connected to a bit line, and the other electrode is connected to the storage capacitor.
FIG. 1 illustrates the construction of a known storage field. Here, only one bit line and a plurality of word lines have been illustrated for the storage field. The word lines are referenced X and the bit line is referenced Y. A storage cell SZ is in each case located at the intersections of the word lines X and the bit lines Y. This storage cell consists of a MOS transistor MS and a storage capacitor CS. The entire storage cell field is divided into two zones B1 and B2. The division is made in that each bit line Y is in each case divided into two halves Y1 and Y2, a read out amplifier LV being arranged between these two halves of the bit line. Therefore, a read out amplifier column is situated between the two cell field zones B1 and B2. The read out amplifiers can be constructed, for example, as pulsed flip-flops as described in the above-mentioned publication.
If the storage cells SZ consist of single-transistor storage cells, the read out signals which arise on the read out of a storage cell are very small. If the storage cells connected to a word line are selected, and thus the control inputs of the transistors MS which are connected to the word line are supplied with a signal which renders these transistors conductive, then as a result of the capacitive coupling between the word lines and the bit lines, interference signals are coupled over to the bit lines. These interference signals are superimposed upon the read out signals, so that often it is impossible to analyze the read out signals. For this reason, blank cells are provided, with the aid of which the interference signals which are coupled to the bit lines through the selection of the word line are to be compensated. Here, such a blank cell LZ is provided on each side of the read out amplifier LV in each half of the bit line. This cell consists, like the storage cell SZ, in each case of a transistor MD and a storage capacitor CD. The connection between the transistor MD and the storage capacitor CD is also connected to a generator G.
With the aid of the blank cell LZ which forms a blank cell column DS, the interferences which are coupled to the bit lines due to the selection of the word lines are now compensated. The operation is as follows: Prior to the call-up of a word line of the cell field, the capacitors CD of the blank cells are charged by the generator G to a voltage which lies between the zero signal level and the one signal level of the storage cells. On the call up of a word line, the blank cells arranged in the other cell zone are also called up. If, for example, the word line X1 is operated, the blank cells LZ located in the cell zone are then likewise operated by a signal on the line XDR. This is illustrated in FIG. 2. As a result of the selection of the word line X1, interferences arise on the bit line half Y1 and as a result of the selection of the line XDR of the blank column DS, interferences occur on the bit line half Y2. These interferences are fed to the read out amplifier LV and can thus be compensated. Naturally, corresponding things apply when the word line XN is operated. Then, at the same time, the line XDL of the blank cell column DS1 is selected.
The known arrangement illustrated in FIG. 1 has the disadvantage that an additional generator G is required in order to produce the mean voltage across the storage capacitors CD of the blank cells. This generator must be able to compensate component fluctuations, temperature fluctuations and supply voltage fluctuations. In addition, the interferences caused by the word lines act as a push-push interference on the read-out amplifiers, whose operating point is thus displaced.